update qtls

vendor/github.com/cloudflare/sidh/internal/utils/cpu.go

@@ -0,0 +1,11 @@
+package utils
+
+type x86 struct {
+	// Signals support for MULX which is in BMI2
+	HasBMI2 bool
+
+	// Signals support for ADX
+	HasADX bool
+}
+
+var X86 x86

vendor/github.com/cloudflare/sidh/internal/utils/cpuid_amd64.go

@@ -0,0 +1,29 @@
+// +build amd64,!noasm
+
+// Sets capabilities flags for x86 according to information received from
+// CPUID. It was written in accordance with
+// "Intel® 64 and IA-32 Architectures Developer's Manual: Vol. 2A".
+// https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-2a-manual.html
+
+package utils
+
+// Performs CPUID and returns values of registers
+// go:nosplit
+func cpuid(eaxArg, ecxArg uint32) (eax, ebx, ecx, edx uint32)
+
+// Returns true in case bit 'n' in 'bits' is set, otherwise false
+func bitn(bits uint32, n uint8) bool {
+	return (bits>>n)&1 == 1
+}
+
+func init() {
+	// CPUID returns max possible input that can be requested
+	max, _, _, _ := cpuid(0, 0)
+	if max < 7 {
+		return
+	}
+
+	_, ebx, _, _ := cpuid(7, 0)
+	X86.HasBMI2 = bitn(ebx, 8)
+	X86.HasADX = bitn(ebx, 19)
+}

vendor/github.com/cloudflare/sidh/internal/utils/cpuid_amd64.s

@@ -0,0 +1,13 @@
+// +build amd64,!noasm
+
+#include "textflag.h"
+
+TEXT ·cpuid(SB), NOSPLIT, $0-4
+    MOVL eaxArg+0(FP), AX
+    MOVL ecxArg+4(FP), CX
+    CPUID
+    MOVL AX, eax+8(FP)
+    MOVL BX, ebx+12(FP)
+    MOVL CX, ecx+16(FP)
+    MOVL DX, edx+20(FP)
+    RET